Computer systems, from small handheld electronic devices to medium-sized mobile and desktop systems to large servers and workstations, are becoming increasingly pervasive in our society. Computer systems typically include one or more processors. A processor manipulates and controls the flow of data in a computer by executing instructions. Increasing the speed at which instructions are executed tends to increase the computational power of the computer. Processor designers employ many different techniques to increase processor speed to create more powerful computers for consumers. One such technique is to implement a pipeline in a processor.
A pipeline is an assembly line for instructions. When an instruction is issued to a processor pipeline, the instruction is progressively processed through separate stages in the pipeline. At any given moment, the pipeline may contain many instructions, each at different stages of processing at different stages in the pipeline. In this manner, processor resources are better utilized, thereby increasing instruction execution throughput by the processor.
The execution of one instruction in a pipeline may depend on the execution of one or more previously issued instructions. If data from a first instruction in a pipeline is needed by a second instruction in the pipeline, then the unavailability of the data from the first instruction causes a delay in the execution of the second instruction. In such a case, a portion of the pipeline may need special processing, such as being halted, or stalled, until the first instruction completes execution so the resulting data can be used by the second instruction. This condition is called a hazard.
For example, consider the following set of instructions:
load X.fwdarw.R1 PA1 add R1+R2.fwdarw.R3 PA1 load X.fwdarw.R1 PA1 add R2+R3.fwdarw.R1
Proper execution of the add instruction depends on proper execution of the load instruction because the add instruction requires the data in register R1 as an operand, and the load instruction must first load this data into R1. Unfortunately, the result of the load instruction may not be ready by the time the add instruction is ready to use it. Consequently, execution of the add instruction must be delayed until the load instruction is completed. This is known as a read after write (RAW) hazard because the add instruction must read register R1 after the load instruction writes to register R1.
Now consider the following set of instructions:
Proper execution of the add instruction no longer depends on the load instruction because the target of the load instruction, R1, is not an operand of the add instruction. R1 is, however, the target of the add instruction, and subsequent instructions that read from register R1 expect R1 to contain the sum of R2+R3 rather than the data loaded by the load instruction. Unfortunately, the load instruction may take longer to execute than the add instruction. Consequently, execution of the add instruction may need to be delayed until the load instruction is completed so that the load instruction does not overwrite its return data in place of R2+R3 in register R1. This is known as a write after write (WAW) hazard because the add instruction must write to register R1 after the load instruction writes to R1.